C:/Documents and Settings/Prathima Agrawal/My Documents/PAPERS/2007/VTS07/BOSE/PAP/haz.dvi

Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, are easily invalidated by hazards. The invalidation of non-robust tests occurs primarily due to non-zero delays of off-path circuit elements. Thus, non-robust tests are of limited value when process variations cause gate delays to vary. We propose a bounded gate delay model for test quality evaluation and give a novel simulation algorithm that is less pessimistic than previous approaches. The key idea is that certain time-correlations among the multiple transitions at the inputs of a gate cannot cause hazard at its output. We maintain “ambiguity lists” at all nodes. These lists are propagated along with events, similar to fault lists in the traditional concurrent fault simulation. They are used to suppress erroneous unknown states. Experimental results for ISCAS benchmarks with gate delay variation of ±15% show a miscorrelation of the critical path delay by as much as 20%.